Field of the Invention
This invention relates to phase-locked loops and more particularly to control of phase-locked loops.
Description of the Related Art
Digital phase-locked loops (PLLs) require digital control of an oscillator. Several approaches to achieving such digital control are described in R. B. Staszewski, et. al., “All-Digital TX Frequency Synthesizer and Discrete-Time Receiver for Bluetooth Radio in 130-nm CMOS”, JSSC, Volume 39, No 12, December 2004 pp. 2278-2291; C.-M. Hsu, M. Z. Straayer, M. H. Perrott, “A Low-Noise Wide-BW 3.6-GHz Digital Delta-Sigma Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation,” IEEE J. Solid-State Circuits, vol. 43, December 2008, pp. 2776-2786; and M. H. Perrott, Y. Huang, R. T. Baird, B. W. Garlepp, D. Pastorello, E. T. King, Q. Yu, D. B. Kasha, P. Steiner, L. Zhang, J. Hein, B. Del Signore, “A 2.5 Gb/s Multi-Rate 0.25 μm CMOS Clock and Data Recovery Circuit Utilizing a Hybrid Analog/Digital Loop Filter and All-Digital Referenceless Frequency Acquisition,” IEEE J. Solid-State Circuits, vol. 41, December 2006, pp. 2930-2944.
In Hsu, a Digital-to-Analog Converter (DAC) is used to control an analog varactor, with segmentation into coarse and fine sections being employed to reduce design complexity while achieving excellent noise performance. However, that approach requires a relatively high resolution, low noise DAC implementation to prevent degradation of the oscillator's phase noise due to the large gain, defined as Kv, of the voltage-to-frequency characteristic occurring with such varactor tuning. A related approach is shown in Perrott, in which the use of a DAC for frequency control is complemented with a purely analog control path and an expander circuit that improves the linearity of the oscillator frequency control. The purely analog control path sets the overall PLL bandwidth, and allows the DAC-controlled path to have much lower bandwidth to allow for an easier DAC implementation and improved filtering of noise. However, this approach ends up being fairly complex from an analog implementation standpoint, and can lead to increased power and area requirements when excellent noise performance is required. In Staszewski, analog control of varactor(s) is avoided by instead dithering the varactor control voltage between high and low values. That approach avoids the need for a DAC, but requires small varactor sizes in order to prevent the quantization noise produced by dithering from degrading the oscillator's phase noise. In turn, the small varactor size requires a large number of varactors be employed to achieve a reasonably wide frequency tuning range for the oscillator. As such, an important concern in this all-digital approach is managing the complexity of the switch network that controls the high/low settings of each of the many varactors.
Accordingly, improvements in oscillator control are desirable.